A programmable logic circuit such as a FPGA or reconfigurable logic is known as a device that can perform different circuit operations by having a plurality of logic blocks that perform logic operation processing and changing a connection state between the plurality of logic blocks programmable.
Meanwhile, a gated clock technique of stopping a clock supply to a flip-flop (hereinafter, referred to as FF) or the like that does not need to operate is known as a technique for reducing power consumption in a circuit that is used in a system such as a mobile terminal. Another known technique for reducing power consumption in a circuit is a technique (hereinafter, referred to as power-off technique) of reducing a leak current by setting a switch arranged between a power supply and a module OFF according to need.
By applying the gated clock technique and the power-off technique for reducing power consumption to a programmable logic circuit, a low-power consumption programmable logic circuit can be realized (refer to a patent document 1, for example). When realizing the low-power consumption programmable logic circuit, clock skew poses a problem.
Here, the clock skew will be described.
In a synchronous design method that is currently often used in LSI (Large Scale Integration) design, a clock signal for controls is applied, for example, to registers with a same timing. In actual LSI, a difference of a delay, which is caused in a clock signal between a clock generation source and a register (hereinafter, referred to as clock delay), may occur between registers because of a structure difference of a clock supply circuit. This delay difference is called clock skew. If clock skew having a predetermined period of time or longer occurs, an error is caused in transfer of data between registers, resulting in an operational defect in the programmable logic circuit.
The following describes an operational defect in a programmable logic circuit caused by clock skew, with reference to FIGS. 12, 13A and 13B. FIGS. 12, 13A and 13B illustrate a situation where the operational defect in the programmable logic circuit is caused by the clock skew. Note that FIG. 13A shows a case in which transfer of data is correctly performed between a register 1001 and a register 1002, and FIG. 13B shows a case in which transfer of data is not correctly performed between the register 1001 and the register 1002.
In a circuit example shown in FIG. 12, output data from the register 1001 is inputted to the register 1002 as input data. A clock signal CLK1 and a clock signal CLK2 are inputted to the register 1001 and the register 1002 respectively.
A time from when the clock signal CLK1 rises to when the clock signal CLK2 rises (a delay difference between the clock signal CLK1 and the clock signal CLK2) is each of T1001 and T1011. Also, a time from when the clock signal CLK1 rises to when an input to the register 1002 varies is each of T1002 and T1012.
In the case of FIG. 13A in which the time T1001 is shorter than the time T1002, the clock signal CLK2 rises before the input to the register 1002 varies as shown in a section R1000. Therefore, data that is retrieved by the register 1002 at the rising edge of the clock signal CLK2 is data that was outputted from the register 1001 before the clock signal CLK1 rises, i.e., data which is to be retrieved by the register 1002 if transfer of data is correctly performed between the registers.
In the case of FIG. 13B in which the time T1011 is longer than the time T1012, the clock signal CLK2 rises after the input to the register 1002 has varied as shown in a section R1010. Therefore, data that is retrieved by the register 1002 at the rising edge of the clock signal CLK2 is data that was retrieved by the register 1001 at the rising edge of the clock signal CLK1. Thus, transfer of data is not correctly performed between the register 1001 and the register 1002.
As mentioned above, if clock skew having a predetermined period of time or longer occurs, an error is caused in transfer of data between registers. Therefore, a delay element for compensating for clock skew is generally inserted between registers to avoid the error caused in transfer of data between registers due to the clock skew.
Patent Document 1: Japanese Published Patent Application No. 2003-174358